One of the most widely used circuits is the Analog-to-Digital Converter (ADC). Accuracy of the conversion from analog to digital is very important and may vary with the size of the input analog signal. These errors can be non-linear and difficult to correct.
FIG. 1A shows a prior-art ADC. Comparator 12 compares its + and − input voltages to generate a comparator output voltage VCOMP. An upper array of capacitors 14, 17, 18 is connected to the + input, while an identical lower array of capacitors 14, 16, 19 is connected to the − input. The capacitors may be binary-weighted or may have other weightings. In this example, the capacitor weights are 1, 1, 2, 3, 5, 10, 17, and 32 times a minimum or unit capacitance value C of a smallest capacitor.
Actual fabricated circuits have variations in sizes of capacitors 14, 16-19 that may cause errors during data conversion. For example, the capacitors may vary by +/−1%. For the smaller or Least-Significant-Bit (LSB) capacitors 14, the impact of this variation is relatively small and produces a tolerable error in the final result. However, for the Most-Significant-Bit (MSB) capacitors 16-19, this 1% size variation can cause a larger linearity error in the final result.
For example, capacitor 17 has a nominal value of 17C, but may have an actual value of 17.12 C. Although this 0.12C error is within the 1% tolerance, 0.12C is 12% of the LSB capacitance of 1C.
Calibration may be used to measure the actual capacitances of MSB capacitors 16-19 to compensate for these linearity errors. It can be assumed that LSB capacitors 14 have ideal weights or sufficient accuracy for the application. During a calibration routine, a Successive-Approximation Register (SAR) applies a sequence of signals to LSB capacitors 14 and VCOMP is examined to see if the SAR setting applied to LSB capacitors 14 produces a higher or lower total capacitance (and voltage swing) than capacitor 17. A reference voltage VREF is applied to capacitor 17 while lower 17C capacitor 16 is grounded. A common-mode voltage VCM such as VREF/2 is applied to both MSB capacitors 18, 19 to ignore this pair. The SAR register drives each pair of LSB capacitors 14 to 0 by applying VREF to the lower capacitor 14 and ground to the upper capacitor 14 of that pair (if VCOMP is logic 1 for this trial), or return to VCM for a 0 state. The SAR settings are tested until a closest match is found. The final SAR setting can be multiplied by the nominal capacitances of the LSB capacitors 14 that are set to 1 and summed to obtain the measured value of 17C formed by capacitors 17, 16.
During calibration, noise may occur due to various sources such as thermal noise in the circuit or system, power-supply noise, or reference-signal noise. This noise tends to be random and can occasionally cause the measured value to jump to a different value. FIG. 1B shows an idealized continuous distribution of measured values for a capacitor being calibrated many times. When the calibration of 17C formed by capacitors 16, 17 is repeated many times, a bell-shaped distribution of measured results may occur due to noise. This bell curve is centered at the actual value of 17C formed by capacitors 16, 17, such as 17.12 C in this example.
FIG. 1C shows a quantized distribution of measured values for a capacitor being calibrated many times. Since the digital results from the ADC are quantized to integer values of C, the measured results are a distribution with a large peak at 17C and a smaller peak at 18C. A weighted average of these two peaks produces the actual value of 17.12 C.
FIG. 2A shows a calibration sequence with little noise. The SAR or other logic initially drives all capacitors 14, 18, 19 to VCM while VREF is applied to 17C capacitor 17 and ground to 17C capacitor 16. Since only 17C capacitor 17 is charged, a differential voltage proportional to the +17.12 C value of 17C formed by capacitors 16, 17 is measured by comparator 12. Note that the voltages shown in FIGS. 2A-2B are idealized voltages, such as a voltage in μV when the unit capacitance C is 1 fF.
Next, the SAR drives the 10C capacitor pair 14 low by driving ground and VREF to the upper and lower 10C capacitors 14. This subtracts a differential voltage proportional to 10C. The resulting voltage +7.12 is greater than 0, so the 10C bit is set to 1 in the SAR.
Next, the SAR drives the 5C capacitor pair 14 low by driving ground and VREF to the upper and lower 5C capacitors 14. This subtracts a differential voltage proportional to 5C. The resulting voltage +2.12 is greater than 0, so the 5C bit is set to 1 in the SAR.
Next, the SAR drives the 3C capacitor pair 14 low by driving ground and VREF to the upper and lower 3C capacitors 14. This subtracts a differential voltage proportional to 3C. The resulting voltage −0.88 is less than 0, so the 3C bit is set to 0 in the SAR. The SAR drives the 3C capacitor pair to the common-mode voltage, (VCM, VCM), since VCOMP went below zero and too much was subtracted. This takes the voltage back up to +2.12.
Then the SAR drives the 2C capacitor pair 14 low by driving ground and VREF to the upper and lower 2C capacitors 14. This subtracts a differential voltage proportional to 2C, or +2.12−2=+0.12. The resulting voltage +0.12 is greater than 0, so the 2C bit is set to 1 in the SAR.
Finally, the SAR drives the 1C capacitor pair 14 low by driving ground and VREF to the upper and lower 1C capacitors 14. This subtracts a differential voltage proportional to 1C. The resulting voltage −0.88 is less than 0, so the 1C bit is set to 0 in the SAR.
The final digital code in the SAR at the end of the calibration sequence is 11010. The weights of LSB capacitors 14 are multiplied by this digital code and summed to obtain the measured value:1×10C+1×5C+0×3C+1×2C+0×1C=17C. 
FIG. 2B shows a calibration sequence with significant noise. For larger ADC's with more significant bits, the noise may be greater than the LSB. In the example of FIG. 2B, noise of −2.0 is injected when the 2C bit is being evaluated during the calibration routine. In FIG. 2A, the idealized voltage read when testing the 2C pair of LSB capacitors 14 is +0.12, but when the −2.0 noise is added the measured voltage by comparator 12 is −1.88 as shown in FIG. 2B.
Since the resulting voltage −1.88 is less than 0, the 2C bit is set to 0 in the SAR. The SAR drives the 2C capacitor pair to the common-mode voltage, (VCM, VCM), since VCOMP went below zero and too much was subtracted. This takes the voltage back up to +2.12.
Finally, the SAR drives the 1C capacitor pair 14 low by driving ground and VREF to the upper and lower 1C capacitors 14. This subtracts a voltage proportional to 1C. The resulting voltage +2.12−1=+1.12 is greater than 0, so the 1C bit is set to 1 in the SAR.
The final digital code in the SAR at the end of the calibration sequence with noise is 11001. The weights of LSB capacitors 14 are multiplied by this digital code and summed to obtain the measured value:1×10C+1×5C+0×3C+0×2C+1×1C=16C. 
The noise caused the measurement to be off by more than one significant bit, as 16C is more that 1.00 less than the actual value of 17.12 in this example. Even worse, this error can accumulate to other MSB's when they are later calibrated using the erroneous value for 17C formed by capacitors 16, 17.
FIG. 3 is a plot of the spectral density of an ADC before calibration. The decibels relative to full scale (dBFS) of the Power Spectral Density (PSD) is plotted from a Fast Fourier Transformer (FFT) of a simulation of a typical ADC before calibration. Capacitor mismatch causes spurs 302 in the spectrum. These spurs 302 are undesirable. Calibration can improve the plot and reduce the size of spurs 302 when the noise is less than a significant bit, but when the noise is greater than the LSB, spurs 302 can remain even after calibration. Many calibration methods limit ADC accuracy or conversion rate, require special input signals such as sine or triangular waves, are complex and require a large chip area and power, with a higher manufacturing cost. Calibration accuracy is often susceptible to system noise.
What is desired is a high-resolution ADC or Digital-to-Analog Converter (DAC) with good linearity so that the digital output closely follows the analog input, or vice-versa. It is desired to reduce spurs in the frequency domain that are caused by ratiometric error in matching digital/analog conversion elements such as capacitors in a weighted-capacitor array. It is further desired to remove the effects of noise during calibration that can inject significant errors in the calibrated capacitor ratios. It is desired to reduce such noise errors to prevent them from accumulating into higher-significance bits during calibration sequences. Calibration of a SAR-ADC in a noisy environment is desirable.